Split gate nonvolatile memory cell devices are known. For example, U.S. Pat. No. 7,315,056 discloses a split-gate nonvolatile memory cell device, which is incorporated herein by reference for all purposes. The channel region is defined between a source and a drain formed in a semiconductor substrate. A first part of the channel region is controlled by a floating gate, while a second part of the channel region is controlled by a select gate. An erase/program gate is disposed over the source region. The memory cells can be formed on the planar surface of the substrate, or around fin shaped portions of the substrate to increase current flow, such as U.S. Pat. No. 8,461,640 (a FinFET configuration), which is incorporated herein by reference for all purposes.
It is also known to form logic (CMOS) devices on the same wafer substrate as the non-volatile memory cells. See for example, U.S. Pat. No. 9,276,005. However, processing steps in forming the memory cells can adversely affect the previously fabricated logic devices, and vice versa. Moreover, as device geometries continue to shrink, it is difficult to form logic and memory devices on the same substrate with each providing the desired performance.